In some semiconductor manufacturing processes, such as "flip chip", bumps are fabricated on pad areas of a semiconductor die in order to interconnect the die to a package. There are various techniques for forming the bumps, such as for example, the C4 (Controlled Collapse Chip Connection) bump process or the E3 (Extended Eutectic Evaporative) bump process. These two processes use a bump made of a solder that is very high in lead content. For example, in the C4 process, approximately 97% of the solder composition is lead. Also, for the E3 process, the solder balls are soft and can be easily deformed. These two evaporative processes can be expensive to fabricate, adding to manufacturing costs.
Electroless and electroplating processes have been developed to form bumps that are made of a harder material and can be fabricated at a much lower cost than either E3 or C4. The bumps are formed of a solder having a composition that makes the bumps relatively harder. For example, a eutectic solder is composed of approximately 63% tin and 37% lead and is harder than the solder used in the E3 or C4 processes.
One problem with the known bump forming technologies, and in particular the electroless and electroplating bump forming processes, is that thermal stress, such as in a solder reflow process step, can create areas of stress which can cause cracks to form. The cracks form in the passivation layer where the solder bump contacts the aluminum pad and the cracks may propagate into the semiconductor die causing failure of the device.
Generally, in the electroless process, a passivation layer is deposited over the metal pad. An opening is formed in the passivation layer to allow a solder joint to be formed on the metal pad. In some embodiments, a polyimide layer may also be formed over the passivation layer. The polyimide layer is pulled back from the edge of the passivation layer. A problem occurs because the solder bump under bump metal (UBM), where it is formed over the passivation layer, does not adhere to the passivation layer. This causes an area of stress at the edge of the passivation layer over the metal pad. As the die is heated and subsequently cooled in the manufacturing process, cracks can develop in the passivation layer, or craters can form in the semiconductor material, at this high stress area, potentially causing complete failure of the semiconductor device. Likewise, in the electroplating process, stress areas can develop at the interfaces of the various materials having different thermal coefficients of expansion. Cracks can develop at these stress areas causing failure of semiconductor device.
Therefore, a need exists for reducing these high stress areas in solder bump formation.